Monthly Archives: February 2011

Viterbi Decoder, Traceback

Posted on February 20, 2011 by webmaster

There are two basic ways to keep track of the best path to get to each state.  These are the register-exchange, and the traceback method.  The register exchange is very easy to understand, and works well for small constraint lengths.  … Continue reading →

Posted in FPGA, VHDL | Tagged | Comments Off on Viterbi Decoder, Traceback

Viterbi Decoder, ACS

Posted on February 20, 2011 by webmaster

The first part of the Viterbi Decoder is simply tracking the best path to each possible state.  This is the main complex part of the viterbi decoder, as it requires several accumulators.  Each ACS unit is fairly simple, but there … Continue reading →

Posted in FPGA, VHDL | Tagged | Comments Off on Viterbi Decoder, ACS

Convolutional Coding

Posted on February 19, 2011 by webmaster

Convolutional Coding is a form of error correction code that is fairly popular because of the fairly low decoding complexity, and because there are popular algorithms that accept soft inputs.  The encoding complexity for convolutional codes is extremely low as … Continue reading →

Posted in FPGA, VHDL | Tagged , | Comments Off on Convolutional Coding

Overpipelining Predicates

Posted on February 10, 2011 by webmaster

A previous post discussed why overpipelining occurs.  Overpipelinig was defined as adding register stages for no logicial or performance reason, but simply as a code convenience.  It is a common issue with design styles that favor single clocked processes.  Subexpressions … Continue reading →

Posted in FPGA, Verilog | Comments Off on Overpipelining Predicates

Overpipelining

Posted on February 5, 2011 by webmaster

There are a handful of popular coding styles for VHDL/Verilog.  The best examples of the two prevalent ones can be seen with state machines.  The academic books like to show everything as two processes — one combinatorial, one sequential.  A … Continue reading →

Posted in Verilog, VHDL | Comments Off on Overpipelining

Misusing Simulations

Posted on February 5, 2011 by webmaster

Simulations are a wonderful tool for verification, and for debugging problems.  There is a fine line between using simulation for debugging, and misusing simulation as a design aid.  When simulation is done for debug the intent is to find things … Continue reading →

Posted in FPGA, Fundamentals | Comments Off on Misusing Simulations

Deceptive DDS Tables, Part 2

Posted on February 1, 2011 by webmaster

Generating DDS tables was the topic of a previous post. I decided to go a bit further with my analysis.  I decided to compare the two quarter-table generating methods to see which one had better properties in terms of robustness … Continue reading →

Posted in Math | Comments Off on Deceptive DDS Tables, Part 2