Author Archives: webmaster

VHDL Procedures

Posted on February 11, 2014 by webmaster

Procedures can be useful for more than just simulation.

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Exporting Hierarchy from Vivado

Posted on February 17, 2013 by webmaster

Xilinx recently released a webpack for Vivado.  This is an excellent way to start learning how to get the most out of the new features.

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VHDL and Division vs Shifting

Posted on February 7, 2013 by webmaster

This is a short post.  Tools like XST do support division by powers of two for numeric types in VHDL.  However, VHDL defines division in a mathematically consistent way, which is not the same as C.  

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Inferring Multiple BRAMs

Posted on April 9, 2012 by webmaster

The width-changing buffer is a very common type of design.  It can be generated from coregen, but coregen only generates NGC files for the simple RAMs.  This becomes an issue if you want something to be configurable.  It also means … Continue reading →

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SSH Host-Key Setup

Posted on April 3, 2012 by webmaster

SSH host-keys can be a convenience, or can (potentially) increase security.  Assuming it never becomes easy to directly defeat the encryption used by SSH, someone would need to know your username/password.  With host-keys, they would also (likely) need to have … Continue reading →

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Numeric_Std vs Std_Logic_Unsigned

Posted on March 31, 2012 by webmaster

One of VHDL’s annoyances is the excessive typing.  It’s one of the things VHDL got wrong.  As a result, two competing solutions were developed.  Sadly, neither is perfect.

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Creative Uses of Addition

Posted on March 27, 2012 by webmaster

I’ve never been a fan of VHDL’s numeric_std.  It makes a distinction between unsigned, signed, and std_logic_vector for the addition operation.  The operation is (or should be) the same in all cases.  My main issue is that over half of … Continue reading →

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Sandbox, Bit Counting

Posted on March 25, 2012 by webmaster

Bit-counting is a rare operation.  This makes it a good candidate for sandboxing — it isn’t clear what the best way to express the problem will be.  This article looks at four different ways to express the bit-couting operation with … Continue reading →

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Using GIT to Manage Builds

Posted on December 17, 2011 by webmaster

One issue with large FPGA projects is the long build time.  With methods like SmartXplorer, Xilinx’s “build baby build” tool for trying multiple placement options, build can often take hours to complete.  During a build, there is a lot an … Continue reading →

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Mixing LFSRs

Posted on August 28, 2011 by webmaster

This was a topic of minor importance that came up recently with a college.  LFSR’s have been discussed here in the past.  One of the interesting aspects of LFSR’s is that the XOR of any two (or more) bits within … Continue reading →

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