Procedures can be useful for more than just simulation.
Xilinx recently released a webpack for Vivado. This is an excellent way to start learning how to get the most out of the new features. Continue reading
This is a short post. Tools like XST do support division by powers of two for numeric types in VHDL. However, VHDL defines division in a mathematically consistent way, which is not the same as C. Continue reading
The width-changing buffer is a very common type of design. It can be generated from coregen, but coregen only generates NGC files for the simple RAMs. This becomes an issue if you want something to be configurable. It also means lots of simple cores. This article shows three possible coding styles and how they differ in implementation. Continue reading
SSH host-keys can be a convenience, or can (potentially) increase security. Assuming it never becomes easy to directly defeat the encryption used by SSH, someone would need to know your username/password. With host-keys, they would also (likely) need to have a specific file. In the more convenient case, you can also choose to have no password and instead rely on access to the file for security. This article is targeted towards the latter. Continue reading
One of VHDL’s annoyances is the excessive typing. It’s one of the things VHDL got wrong. As a result, two competing solutions were developed. Sadly, neither is perfect.
I’ve never been a fan of VHDL’s numeric_std. It makes a distinction between unsigned, signed, and std_logic_vector for the addition operation. The operation is (or should be) the same in all cases. My main issue is that over half of the time, I don’t personally consider the vector to represent a number. This article is to show a few cases where the additions clearly don’t have numeric arguments.
Bit-counting is a rare operation. This makes it a good candidate for sandboxing — it isn’t clear what the best way to express the problem will be. This article looks at four different ways to express the bit-couting operation with unexpected results.
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One issue with large FPGA projects is the long build time. With methods like SmartXplorer, Xilinx’s “build baby build” tool for trying multiple placement options, build can often take hours to complete. During a build, there is a lot an FPGA developer could do, but this would result in the bitfile not matching the newly revised code. What I’ve always wanted is a way to do a commit of the source code, then retroactively commit the resulting bit file. That way the bitfile matches the code.
This was a topic of minor importance that came up recently with a college. LFSR’s have been discussed here in the past. One of the interesting aspects of LFSR’s is that the XOR of any two (or more) bits within the LFSR will not create a unique pattern — merely shift the current pattern in phase.
