Category Archives: Fundamentals

Fundamentals of digital logic.

Numeric_Std vs Std_Logic_Unsigned

Posted on March 31, 2012 by webmaster

One of VHDL’s annoyances is the excessive typing.  It’s one of the things VHDL got wrong.  As a result, two competing solutions were developed.  Sadly, neither is perfect.

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Creative Uses of Addition

Posted on March 27, 2012 by webmaster

I’ve never been a fan of VHDL’s numeric_std.  It makes a distinction between unsigned, signed, and std_logic_vector for the addition operation.  The operation is (or should be) the same in all cases.  My main issue is that over half of … Continue reading →

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Misusing Simulations

Posted on February 5, 2011 by webmaster

Simulations are a wonderful tool for verification, and for debugging problems.  There is a fine line between using simulation for debugging, and misusing simulation as a design aid.  When simulation is done for debug the intent is to find things … Continue reading →

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The Value of Nothing()

Posted on January 30, 2011 by webmaster

A recent thedailywtf posting caught my attention because of the number of people who made fun of functions that literally do nothing.  More specifically, functions that directly pass the input to the output.  There were a few other trivial functions … Continue reading →

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Xilinx’s ISIM and TCL

Posted on August 28, 2010 by webmaster

In Xilinx’s ISE 11, isim is another of the tools that was made by people who didn’t intend on using them.  At least, not in the way they would be advertised to the end user.  Really, the disconnect between the … Continue reading →

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Precomputing Logic

Posted on August 11, 2010 by webmaster

One of the most powerful optimizations is the ability to make assumptions about inputs to a system. In this article, timing is met when a comparison is precomputed. This basic method often improves timing. The cost is that assumptions on … Continue reading →

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Hold Violations

Posted on August 10, 2010 by webmaster

A hold violation occurs when the data into a system changes too soon after a clock edge.  Many standards and ICs specify significantly positive hold times.  Failure to meet these hold times can result in unpredictable behavior.

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Negative Setup Time

Posted on August 10, 2010 by webmaster

These registers have not enlisted the aid of a prominent psychic. Continue reading →

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The Carry-Select Method

Posted on August 10, 2010 by webmaster

One method that can be used to optimize a design for performance is based on the carry-select adder.  The general idea is that an adder can either have a carry-in of 0, or a carry-in of 1.  Two adders can … Continue reading →

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Why Asynchronous Signals are Dangerous

Posted on August 10, 2010 by webmaster

The careless use of asynchronous signals can lead to unpredictable operation at any clock frequency. Continue reading →

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