In Xilinx’s ISE 11, isim is another of the tools that was made by people who didn’t intend on using them. At least, not in the way they would be advertised to the end user. Really, the disconnect between the people developing tools and the people who use them is a common theme in EDA. Isim does have one very nice feature — it has a TCL interface. Modelsim and many other tools also have TCL interfaces.
Isim, in ISE 11, was an annoying tool. Mainly because of the poor integration into ISE. It was a seperate application that could be launched from ISE. If there was a flaw found though sim, it required the user to close isim, answer “yes I want to exit” and “no I don’t want to save”, then change the code and relaunch. It didn’t remember settings, and while you could save settings, you had to name a file and then re-open the file each time.
Thus, for a development aid, its GUI was cumbersome. For an automated tool, a GUI isn’t really necessary. Thus it didn’t really seem to be well suited to normal usage. This article describes my first attempt to get isim to work as an automated test. Though I’m new to TCL, the results were promising.
First, from the CLI, isim can be used as follows:
> fuse -prj my_sim.prj > my_sim.exe -tclbatch my_sim.tcl
Where my_sim.prj is essentially a listing of hdl files (the ../’s are due to my directory structure):
vhdl work ../../lib/rs_encoder/rs_encoder_pkg.vhd vhdl work ../../lib/rs_encoder/rs_encoder.vhd vhdl work ../../lib/rs_encoder/rs_encode_logic.vhd vhdl work ../reed_solomon_tb.vhd
The .tcl file is the TCL script that will be run to perform the sim. In my case, I wanted to perform two basic checks — the validated output data was the same as the validated input data, and the output data marked as “last” occurred at the end of a message only. This is a fairly basic test. One of the difficulties with testing is realizing how many ways things can go wrong — often without being initially noticed.
The results of my TCL script are shown below:
# the end result: Finished circuit initialization process. 1 messages complete 2 messages complete 3 messages complete 4 messages complete 5 messages complete 6 messages complete 7 messages complete 8 messages complete 9 messages complete 10 messages complete 11 messages complete 12 messages complete 13 messages complete 14 messages complete 15 messages complete 16 messages complete 17 messages complete Simulation Ended, 4081 good samples.
The idea is to allow automated testing of the RTL’s functionality. This can allow the user to avoid checking in bad code to a revision control system, or at least mark that the commit has known bugs.
One important step with unit tests is to at least test one failing case. Even doing this isn’t really enough to verify that all possible error cases will be caught. Its often dangerous to be the same person writing the HDL, as well as the tests for the HDL. The developer knows how his HDL was intended to be used, and will often test with a narrow focus. Likewise, the developer has an interpretation of the spec which must be correct. Otherwise the testing will be valid, but the end product will not.
In my case, I tried a sim with 9 errors injected into my 8 error correcting Reed-Solomon Decoder:
Finished circuit initialization process. Simulation Error at 3302 ns, 00110001 got instead of 00000000. Simulation Error at 3306 ns, 00010000 got instead of 00000001. Simulation Error at 3310 ns, 01010111 got instead of 00000010. Simulation Error at 3594 ns, 10000000 got instead of 01001001. Simulation Error at 3626 ns, 00010101 got instead of 01010001. Simulation Error at 3922 ns, 00000011 got instead of 10011011. Simulation Error at 3982 ns, 11100100 got instead of 10101010. Simulation Error at 4202 ns, 10100100 got instead of 11100001. Simulation Error at 4238 ns, 00010101 got instead of 11101010. Simulation Error at 4242 ns, 00010100 got instead of 11101011. Simulation Ended, 226 good samples.
As expected, the automated sim quickly finishes, reporting multiple errors. In this case, the attempt to correct 9 errors has actually led to the output having more than 9 errors.
The TCL script is provided below. The main line is “isim condition add {Clk == 1} {“. From this point, there can be if-else statements to compare values. I originally only wanted to look for clock cycles with valid data, but had issues when multiple isim conditions had “Clk == 1” as a condition.
One thing to note is that in the isim condition line, signals in the current scope can be directly accessed. But once inside the code block portion, such objects no longer exist directly. Thus I have several lines with “[show value my_signal]” in order to solve this problem.
The remainder of the files can be found on the Reed-Solomon Encoder, and Reed-Solomon Decoder pages. The files below are the ones for this article.
- VHDL: Reed-Solomon Testbench
- BASH: Reed-Solomon Regression Test
- TCL: Reed-Solomon Regression Test TCL Script
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