Monthly Archives: March 2012

Numeric_Std vs Std_Logic_Unsigned

Posted on March 31, 2012 by webmaster

One of VHDL’s annoyances is the excessive typing.  It’s one of the things VHDL got wrong.  As a result, two competing solutions were developed.  Sadly, neither is perfect.

Posted in Fundamentals, VHDL | Comments Off on Numeric_Std vs Std_Logic_Unsigned

Creative Uses of Addition

Posted on March 27, 2012 by webmaster

I’ve never been a fan of VHDL’s numeric_std.  It makes a distinction between unsigned, signed, and std_logic_vector for the addition operation.  The operation is (or should be) the same in all cases.  My main issue is that over half of … Continue reading →

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Sandbox, Bit Counting

Posted on March 25, 2012 by webmaster

Bit-counting is a rare operation.  This makes it a good candidate for sandboxing — it isn’t clear what the best way to express the problem will be.  This article looks at four different ways to express the bit-couting operation with … Continue reading →

Posted in FPGA, VHDL | Comments Off on Sandbox, Bit Counting