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Category Archives: VHDL
VHDL and Division vs Shifting
This is a short post. Tools like XST do support division by powers of two for numeric types in VHDL. However, VHDL defines division in a mathematically consistent way, which is not the same as C.
Posted in VHDL
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Numeric_Std vs Std_Logic_Unsigned
One of VHDL’s annoyances is the excessive typing. It’s one of the things VHDL got wrong. As a result, two competing solutions were developed. Sadly, neither is perfect.
Posted in Fundamentals, VHDL
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Sandbox, Bit Counting
Bit-counting is a rare operation. This makes it a good candidate for sandboxing — it isn’t clear what the best way to express the problem will be. This article looks at four different ways to express the bit-couting operation with … Continue reading
Viterbi Decoder, Traceback
There are two basic ways to keep track of the best path to get to each state. These are the register-exchange, and the traceback method. The register exchange is very easy to understand, and works well for small constraint lengths. … Continue reading
Viterbi Decoder, ACS
The first part of the Viterbi Decoder is simply tracking the best path to each possible state. This is the main complex part of the viterbi decoder, as it requires several accumulators. Each ACS unit is fairly simple, but there … Continue reading
Convolutional Coding
Convolutional Coding is a form of error correction code that is fairly popular because of the fairly low decoding complexity, and because there are popular algorithms that accept soft inputs. The encoding complexity for convolutional codes is extremely low as … Continue reading
Overpipelining
There are a handful of popular coding styles for VHDL/Verilog. The best examples of the two prevalent ones can be seen with state machines. The academic books like to show everything as two processes — one combinatorial, one sequential. A … Continue reading
Stylizer Script
One of the large issues with code generation is getting unreadable results. Very long lines are easily generated because it’s easy to describe bit-by-bit operations algorithmically. This is very true of LDPC and other ECC codes. I decided to make … Continue reading
Adding Python to VHDL
From previous articles, it might be obvious that I’m a fan of code-generation over the language features in VHDL. This is mainly because the vendors are always slow to adopt any existing parts of the VHDL standard. Further, portability is … Continue reading
Variables and Simulations
I typically design my VHDL components for ease of reuse. I like things that are easy to read/write and infer a clear structure. As such, I try to avoid variables as much as possible. This is because VHDL doesn’t allow … Continue reading