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Category Archives: Verilog
Verilog’s Casex Issue
Verilog also has some academic constructs. Things that make sense for people who don’t want to design a structure. Casex is one example from Verilog.
Posted in Verilog
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Overpipelining Predicates
A previous post discussed why overpipelining occurs. Overpipelinig was defined as adding register stages for no logicial or performance reason, but simply as a code convenience. It is a common issue with design styles that favor single clocked processes. Subexpressions … Continue reading
Overpipelining
There are a handful of popular coding styles for VHDL/Verilog. The best examples of the two prevalent ones can be seen with state machines. The academic books like to show everything as two processes — one combinatorial, one sequential. A … Continue reading
Stylizer Script
One of the large issues with code generation is getting unreadable results. Very long lines are easily generated because it’s easy to describe bit-by-bit operations algorithmically. This is very true of LDPC and other ECC codes. I decided to make … Continue reading
Verilog Code Generator
In a previous article, I released a VHDL code generator written in python and using python as the embedded language. That generator worked fairly cleanly, adding constructs that mostly looked like VHDL code. I decided to try a different approach … Continue reading
Inferring DSP48 slices in Verilog
The full DSP48E1 component has so many ports that Xilinx has started making “macro” primitives for common DSP48 uses. The DSP48E1 in the Virtex-6 has a lot of advanced features. XST supports inferring multipliers, and there are even some code … Continue reading