Welcome
Welcome to cdstahl.orgCategories
-
Recent Posts
- VHDL Procedures
- Exporting Hierarchy from Vivado
- VHDL and Division vs Shifting
- Inferring Multiple BRAMs
- SSH Host-Key Setup
- Numeric_Std vs Std_Logic_Unsigned
- Creative Uses of Addition
- Sandbox, Bit Counting
- Using GIT to Manage Builds
- Mixing LFSRs
- Affine Feedback Shift Register
- Verilog’s Casex Issue
- Linear Regression
- Non-Orthogonal Basis Vectors
- Viterbi Decoder, Traceback
Archives
Meta
Monthly Archives: February 2014
VHDL Procedures
Procedures can be useful for more than just simulation.
Posted in Uncategorized
Comments Off on VHDL Procedures