Monthly Archives: January 2011

Deceptive DDS Tables

Posted on January 31, 2011 by webmaster

The direct digital synthesizer has become a fundamental block in many FPGA based designs.  It is an interesting project to work on, but realistically there isn’t much need to re-write a DDS if you have access to IP from an … Continue reading →

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The Value of Nothing()

Posted on January 30, 2011 by webmaster

A recent thedailywtf posting caught my attention because of the number of people who made fun of functions that literally do nothing.  More specifically, functions that directly pass the input to the output.  There were a few other trivial functions … Continue reading →

Posted in Fundamentals | Comments Off on The Value of Nothing()

Stylizer Script

Posted on January 1, 2011 by webmaster

One of the large issues with code generation is getting unreadable results.  Very long lines are easily generated because it’s easy to describe bit-by-bit operations algorithmically.  This is very true of LDPC and other ECC codes.  I decided to make … Continue reading →

Posted in Verilog, VHDL | Tagged , | Comments Off on Stylizer Script

Verilog Code Generator

Posted on January 1, 2011 by webmaster

In a previous article, I released a VHDL code generator written in python and using python as the embedded language.  That generator worked fairly cleanly, adding constructs that mostly looked like VHDL code.  I decided to try a different approach … Continue reading →

Posted in Verilog | Tagged , | Comments Off on Verilog Code Generator