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Tag Archives: code generation
Stylizer Script
One of the large issues with code generation is getting unreadable results. Very long lines are easily generated because it’s easy to describe bit-by-bit operations algorithmically. This is very true of LDPC and other ECC codes. I decided to make … Continue reading
Verilog Code Generator
In a previous article, I released a VHDL code generator written in python and using python as the embedded language. That generator worked fairly cleanly, adding constructs that mostly looked like VHDL code. I decided to try a different approach … Continue reading
Adding Python to VHDL
From previous articles, it might be obvious that I’m a fan of code-generation over the language features in VHDL. This is mainly because the vendors are always slow to adopt any existing parts of the VHDL standard. Further, portability is … Continue reading