One issue with large FPGA projects is the long build time. With methods like SmartXplorer, Xilinx’s “build baby build” tool for trying multiple placement options, build can often take hours to complete. During a build, there is a lot an FPGA developer could do, but this would result in the bitfile not matching the newly revised code. What I’ve always wanted is a way to do a commit of the source code, then retroactively commit the resulting bit file. That way the bitfile matches the code.
This article aims to show how it is possible to do just this — retroactively commit the synthesis outputs to the already committed source code that was used at the start of the build. For now, I’ll assume that git is installed on a linux machine.
myproj > git init # init only needs to be done once, at the start of the project. myproj > git add *.vhd
The above would be the git commands to create an example project, with three empty files. These are just for an example. For now, lets assume that the user can build from the command line.
myproj > ./build.tcl &
After synthesis gets past the syntax checking, the soruce files can be committed:
myproj > git commit -a
While the build is ongoing, the source files can be modified. Things can be simulated, etc… I’m not entirely sure if you can modify everything. You probably can’t make changes to the UCF file until the build gets to MAP. But it is usually examining, commenting, and simulating the source code that is of interest. Eventually, the build will finish, and you can do:
myproj > git add myproj.bit myproj > git commit --amend
This will retroactively commit the bit file to the previous commit.
As a final note, there may be some issues with modifying source during a build. I suspect that there really isn’t much to worry about — the HDL should have been read in during the first part of synthesis. That said, I probably wouldn’t try making UCF or coregen modifications during the build process, as these might not have been read in during the early phases of the build process.