Category Archives: FPGA

FPGA-specific applications of digital logic.

Exporting Hierarchy from Vivado

Posted on February 17, 2013 by webmaster

Xilinx recently released a webpack for Vivado.  This is an excellent way to start learning how to get the most out of the new features.

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Inferring Multiple BRAMs

Posted on April 9, 2012 by webmaster

The width-changing buffer is a very common type of design.  It can be generated from coregen, but coregen only generates NGC files for the simple RAMs.  This becomes an issue if you want something to be configurable.  It also means … Continue reading →

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Sandbox, Bit Counting

Posted on March 25, 2012 by webmaster

Bit-counting is a rare operation.  This makes it a good candidate for sandboxing — it isn’t clear what the best way to express the problem will be.  This article looks at four different ways to express the bit-couting operation with … Continue reading →

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Using GIT to Manage Builds

Posted on December 17, 2011 by webmaster

One issue with large FPGA projects is the long build time.  With methods like SmartXplorer, Xilinx’s “build baby build” tool for trying multiple placement options, build can often take hours to complete.  During a build, there is a lot an … Continue reading →

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Viterbi Decoder, Traceback

Posted on February 20, 2011 by webmaster

There are two basic ways to keep track of the best path to get to each state.  These are the register-exchange, and the traceback method.  The register exchange is very easy to understand, and works well for small constraint lengths.  … Continue reading →

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Viterbi Decoder, ACS

Posted on February 20, 2011 by webmaster

The first part of the Viterbi Decoder is simply tracking the best path to each possible state.  This is the main complex part of the viterbi decoder, as it requires several accumulators.  Each ACS unit is fairly simple, but there … Continue reading →

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Convolutional Coding

Posted on February 19, 2011 by webmaster

Convolutional Coding is a form of error correction code that is fairly popular because of the fairly low decoding complexity, and because there are popular algorithms that accept soft inputs.  The encoding complexity for convolutional codes is extremely low as … Continue reading →

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Overpipelining Predicates

Posted on February 10, 2011 by webmaster

A previous post discussed why overpipelining occurs.  Overpipelinig was defined as adding register stages for no logicial or performance reason, but simply as a code convenience.  It is a common issue with design styles that favor single clocked processes.  Subexpressions … Continue reading →

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Misusing Simulations

Posted on February 5, 2011 by webmaster

Simulations are a wonderful tool for verification, and for debugging problems.  There is a fine line between using simulation for debugging, and misusing simulation as a design aid.  When simulation is done for debug the intent is to find things … Continue reading →

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Deceptive DDS Tables

Posted on January 31, 2011 by webmaster

The direct digital synthesizer has become a fundamental block in many FPGA based designs.  It is an interesting project to work on, but realistically there isn’t much need to re-write a DDS if you have access to IP from an … Continue reading →

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