Asynchronous control or data signals should generally be avoided. In addition to the well-known metastability issues, there is also a large danger from skew. These problems can cause design failures at any clock rate.
Schematic
Shown above is the relevant registers from a simple state machine. In terms of VHDL, the code for the logic might look like:
...
if (state = IDLE) then
if (trigger = '1') then
next_state <= ACTIVE;
else
next_state <= IDLE;
end if;
elsif (state = ACTIVE) then
...
Which should show the combinatorial logic used to update “state” on the next cycle. For many state machines, “state” will be implemented in a “one-hot” method. Each state will have a register, and exactly one state register will be asserted on any given cycle.
The issue is that an actual implementation of this will require actual elements and routing be used. Skew becomes a very large issue. The larger the clock-data skew at each register affected by “trigger”, the more likely issues are.
Skew issues
The issue shown in the images is that the “trigger” signal arrives at the register for “IDLE” at a different time as the register for “ACTIVE” due to routing issues. In this example, I’m showing a 1.0 ns difference. The clock signal arrives during this 1.0 ns window. The result is that “IDLE” is deasserted — the correct action to transition to the “ACTIVE” state. The “ACTIVE” state register didn’t receive “trigger” before the clock edge, so it remains deasserted. The system has transitioned to an invalid “no state active” and is unlikely to transition from it.
Asynchronous signals should not be used for this reason. If any skew exists, there will be a chance of error. Even at slow rates, there is a chance of failure.