One method that can be used to optimize a design for performance is based on the carry-select adder. The general idea is that an adder can either have a carry-in of 0, or a carry-in of 1. Two adders can be generated, and the correct result selected later. This is a large advantage if there is a large delay in getting the carry-in value. This method uses more resources, and generally works when there are few cases.
Basic Version
As an example, consider the basic problem of an accumulator that can select between two inputs. In order to perform the addition, the correct input must be presented to the adder. This means that the delay to the mux select input should be very low.
Speed Improvement
If two adders are used, the result of both cases can be calculated in parallel. This is also done in parallel with whatever logic is needed to generate the mux select. The clock rate can be increased, though the area is also increased.
I made a quick VHDL project for a similar problem. The logic that generated the mux select was a fairly simple 48 bit comparison.
The result of performing both additions in parallel and selecting the correct one was an increase to 392MHz, from 302MHz. This was post-PAR results for a Xilinx Virtex-6 -1 speed grade part, minimally utilized.