A hold violation occurs when the data into a system changes too soon after a clock edge. Many standards and ICs specify significantly positive hold times. Failure to meet these hold times can result in unpredictable behavior.The below pictures show one issue that can occur when the data changes too quickly after a clock edge.
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- Second Register Clocked
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- Data Arrives Before Clock
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- First Register Clocked
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- Initial
The above images arguably show a setup error — the input is changing before the clock. But the concept is that the data changes too soon after a clock edge. In the above example, the data is able to propagate through two register stages within one clock cycle.
If the setup/hold time isn’t met, the result is that the data may be able to propagate through two register stages. If this normally happens, then serial communications will not be aligned correctly. The alternative is that the data will sometimes be corrupted.
Most low-cost, low speed, synchronous serial protocols specify a positive setup and positive hold time. For an FPGA implementation, it might be tempting to use the clock and internal registers directly. But this will violate the hold-time spec. More thought needs to be put into the design of the interface to ensure both setup and hold times are met. This might mean inverting the output clock, or adding code to a state machine.
It is easy to overlook positive hold time requirement when looking at data on a scope. Its easier to look at the value the data lines have, and the transition of the clock. But to meet spec, the data needs to be held for the hold time.