Category Archives: VHDL

VHDL offers a procedure language construct.  Like most tools, it has a handful of advantages and disadvantages.  Procedures have long been used in simulations to allow complex logic sequences to be represented as a single statement.  This allows the sim … Continue reading →

VHDL makes heavy use of types, and has a concept of an unconstrained vector.  This is a vector whose dimension isn’t specified in the declaration of a construct, but is determined by the instantiation or use of the construct.

VHDL has fairly good support for generics.  VHDL-2008 will actually provide several improvements as well.  Generics are a good alternative to code generation, and work well for the vast majority of designs.  Generics aren’t a complete replacement for code generation … Continue reading →

In a previous article, misuses of variables in processes was discussed. This article describes useful uses of variables in VHDL.

Nonblocking assignments are very common in VHDL.  They have some pitfalls to look out for. VHDL is different from Verilog in that it forces the use of nonblocking assignments for signals.  This means a design will use nonblocking assignments somewhere.

Annoying and Dangerous when misused. Continue reading →