Author Archives: webmaster

Affine Feedback Shift Register

Posted on June 29, 2011 by webmaster

Several previous articles have focused on linear feedback shift registers.  These are very simple circuits which are very often used for generating “maximal” length sequences, which are sequences of all non-zero values of N bits.  “Maximal” does not include the … Continue reading →

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Verilog’s Casex Issue

Posted on June 12, 2011 by webmaster

Verilog also has some academic constructs.  Things that make sense for people who don’t want to design a structure.  Casex is one example from Verilog.

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Linear Regression

Posted on June 9, 2011 by webmaster

Previously, I had written an article about how to use non-orthogonal basis vectors for the modeling of sampled data.  Here I show the same idea, but reformulated as a linear regression problem.

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Non-Orthogonal Basis Vectors

Posted on April 16, 2011 by webmaster

Transforms and projections are often very useful in gaining useful information about a signal.  The Fourier transform is a very common transform that give some information about the frequency content of a signal.  it is not the only possible transform … Continue reading →

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Viterbi Decoder, Traceback

Posted on February 20, 2011 by webmaster

There are two basic ways to keep track of the best path to get to each state.  These are the register-exchange, and the traceback method.  The register exchange is very easy to understand, and works well for small constraint lengths.  … Continue reading →

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Viterbi Decoder, ACS

Posted on February 20, 2011 by webmaster

The first part of the Viterbi Decoder is simply tracking the best path to each possible state.  This is the main complex part of the viterbi decoder, as it requires several accumulators.  Each ACS unit is fairly simple, but there … Continue reading →

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Convolutional Coding

Posted on February 19, 2011 by webmaster

Convolutional Coding is a form of error correction code that is fairly popular because of the fairly low decoding complexity, and because there are popular algorithms that accept soft inputs.  The encoding complexity for convolutional codes is extremely low as … Continue reading →

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Overpipelining Predicates

Posted on February 10, 2011 by webmaster

A previous post discussed why overpipelining occurs.  Overpipelinig was defined as adding register stages for no logicial or performance reason, but simply as a code convenience.  It is a common issue with design styles that favor single clocked processes.  Subexpressions … Continue reading →

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Overpipelining

Posted on February 5, 2011 by webmaster

There are a handful of popular coding styles for VHDL/Verilog.  The best examples of the two prevalent ones can be seen with state machines.  The academic books like to show everything as two processes — one combinatorial, one sequential.  A … Continue reading →

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Misusing Simulations

Posted on February 5, 2011 by webmaster

Simulations are a wonderful tool for verification, and for debugging problems.  There is a fine line between using simulation for debugging, and misusing simulation as a design aid.  When simulation is done for debug the intent is to find things … Continue reading →

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