Category Archives: FPGA

FPGA-specific applications of digital logic.

Another Galois Field Multiply

Posted on August 22, 2010 by webmaster

After completing my Reed-Solomon decoder’s HDL, I decided to see how well it performed.  The results weren’t as good as I expected.  The limiting path was in the field math.  A bit of simple pipelining allowed 250MHz operation on my … Continue reading →

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Division by Multiplication

Posted on August 16, 2010 by webmaster

Occasionally, a value will need to be divided by a non-power of two.  Using the division cores from coregen is an option.  Certainly it is a good option if area isn’t a concern but a quick design time is.  Another … Continue reading →

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Functions Vs Scripts

Posted on August 14, 2010 by webmaster

I recently decided to re-write the logic portion of my Reed-Solomon encoder to use VHDL functions instead of script-generated logic.  I defined a “permute” function to perform the logic manipulation:

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Reed-Solomon Encoder

Posted on August 14, 2010 by webmaster

This article describes how to make a performance optimized Reed-Solomon encoder.  The actual encoder is for an full-length, narrow-sense RS code.  In this case, the code generated was an code that could allow at least 8 bytes to be corrected, … Continue reading →

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The Synthesizer Thanks You For Your Opinion

Posted on August 10, 2010 by webmaster

The synthesizer thanks you for your opinion but has decided to go in another direction. The problem of trying to infer a specific implementation. Continue reading →

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Logically Good, Actually Bad

Posted on August 10, 2010 by webmaster

Often, things that sound like they should work well, but actually don’t.  This actually is related to one of my rules — “avoid excessively creative code.” In this case, I decided to compare the fancy “carry-lookahead” adder to whatever fabric-based … Continue reading →

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