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Deceptive DDS Tables, Part 2
Generating DDS tables was the topic of a previous post. I decided to go a bit further with my analysis. I decided to compare the two quarter-table generating methods to see which one had better properties in terms of robustness … Continue reading
Posted in Math
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Deceptive DDS Tables
The direct digital synthesizer has become a fundamental block in many FPGA based designs. It is an interesting project to work on, but realistically there isn’t much need to re-write a DDS if you have access to IP from an … Continue reading
The Value of Nothing()
A recent thedailywtf posting caught my attention because of the number of people who made fun of functions that literally do nothing. More specifically, functions that directly pass the input to the output. There were a few other trivial functions … Continue reading
Posted in Fundamentals
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Stylizer Script
One of the large issues with code generation is getting unreadable results. Very long lines are easily generated because it’s easy to describe bit-by-bit operations algorithmically. This is very true of LDPC and other ECC codes. I decided to make … Continue reading
Verilog Code Generator
In a previous article, I released a VHDL code generator written in python and using python as the embedded language. That generator worked fairly cleanly, adding constructs that mostly looked like VHDL code. I decided to try a different approach … Continue reading
Better Pipelined Accumulator
As mentioned in a previous article, there is a better was to perform a pipelined addition or accumulation. This method works on the ability of an addition to be efficiently broken up across multiple cycles.
Pipelined Accumulators
In digital design, the ultimate bandwidth is determined by a feedback path. There are a few tricks that can be used to help the situation, but it quickly becomes a losing battle. This article shows one way to allow pipelining … Continue reading
Variable Length Reed-Solomon
Recently, someone had mentioned to me that the thing they liked most about convolutional codes was the ability to just send data in any amount. With convolutional codes, an internal state determines what encoded bits to send. This gives close … Continue reading
Adding Python to VHDL
From previous articles, it might be obvious that I’m a fan of code-generation over the language features in VHDL. This is mainly because the vendors are always slow to adopt any existing parts of the VHDL standard. Further, portability is … Continue reading
Updated Reed-Solomon Encoder
When I originally wrote my Reed-Solomon encoder, I used the basic polynomial long division method directly. This made a lot of sense at the time. It turns out that there is actually a slightly better method.
Posted in FPGA, Math
Tagged code provided, reed solomon
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