Deceptive DDS Tables, Part 2

Posted on February 1, 2011 by webmaster

Generating DDS tables was the topic of a previous post. I decided to go a bit further with my analysis.  I decided to compare the two quarter-table generating methods to see which one had better properties in terms of robustness to truncation of the phase accumulator.  The result were interesting, though easily explained.

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Deceptive DDS Tables

Posted on January 31, 2011 by webmaster

The direct digital synthesizer has become a fundamental block in many FPGA based designs.  It is an interesting project to work on, but realistically there isn’t much need to re-write a DDS if you have access to IP from an FPGA vendor.  This article comes about from looking at one of the most basic DDS optimizations — compressing the sine ROM by using only the first quadrant of the sine wave.

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The Value of Nothing()

Posted on January 30, 2011 by webmaster

A recent thedailywtf posting caught my attention because of the number of people who made fun of functions that literally do nothing.  More specifically, functions that directly pass the input to the output.  There were a few other trivial functions included in the list as well.

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Stylizer Script

Posted on January 1, 2011 by webmaster

One of the large issues with code generation is getting unreadable results.  Very long lines are easily generated because it’s easy to describe bit-by-bit operations algorithmically.  This is very true of LDPC and other ECC codes.  I decided to make a linebreaking script.  Overall, it works OK.  The problem itself can be interesting, and is more an artform.

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Verilog Code Generator

Posted on January 1, 2011 by webmaster

In a previous article, I released a VHDL code generator written in python and using python as the embedded language.  That generator worked fairly cleanly, adding constructs that mostly looked like VHDL code.  I decided to try a different approach with my Verilog code generator, which also works with VHDL.

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Better Pipelined Accumulator

Posted on December 3, 2010 by webmaster

As mentioned in a previous article, there is a better was to perform a pipelined addition or accumulation.  This method works on the ability of an addition to be efficiently broken up across multiple cycles.

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Pipelined Accumulators

Posted on December 1, 2010 by webmaster

In digital design, the ultimate bandwidth is determined by a feedback path.  There are a few tricks that can be used to help the situation, but it quickly becomes a losing battle.  This article shows one way to allow pipelining of the feedback path by exploiting the system’s mathematical properties.  This method is actually not the best way to solve this specific problem, but is slightly more general.  The better solution is presented here.

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Variable Length Reed-Solomon

Posted on November 2, 2010 by webmaster

Recently, someone had mentioned to me that the thing they liked most about convolutional codes was the ability to just send data in any amount.  With convolutional codes, an internal state determines what encoded bits to send.  This gives close to a rate M/N code, depending on the puncturing schedule.  An additional C points are added at the end to allow the last bits to have sufficient error correction.

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Adding Python to VHDL

Posted on October 24, 2010 by webmaster

From previous articles, it might be obvious that I’m a fan of code-generation over the language features in VHDL.  This is mainly because the vendors are always slow to adopt any existing parts of the VHDL standard.  Further, portability is destroyed when the common subset of supported features is considered.

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Updated Reed-Solomon Encoder

Posted on October 12, 2010 by webmaster

When I originally wrote my Reed-Solomon encoder, I used the basic polynomial long division method directly.  This made a lot of sense at the time.  It turns out that there is actually a slightly better method. Continue reading →

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