Category Archives: FPGA

FPGA-specific applications of digital logic.

Better Pipelined Accumulator

As mentioned in a previous article, there is a better was to perform a pipelined addition or accumulation.  This method works on the ability of an addition to be efficiently broken up across multiple cycles.

Posted in FPGA, Math | Tagged | 1 Comment

Pipelined Accumulators

In digital design, the ultimate bandwidth is determined by a feedback path.  There are a few tricks that can be used to help the situation, but it quickly becomes a losing battle.  This article shows one way to allow pipelining … Continue reading

Posted in FPGA, Math | Comments Off on Pipelined Accumulators

Updated Reed-Solomon Encoder

When I originally wrote my Reed-Solomon encoder, I used the basic polynomial long division method directly.  This made a lot of sense at the time.  It turns out that there is actually a slightly better method.

Posted in FPGA, Math | Tagged , | Comments Off on Updated Reed-Solomon Encoder

Inferring DSP48 slices in Verilog

The full DSP48E1 component has so many ports that Xilinx has started making “macro” primitives for common DSP48 uses.  The DSP48E1 in the Virtex-6 has a lot of advanced features.  XST supports inferring multipliers, and there are even some code … Continue reading

Posted in FPGA, Verilog | Comments Off on Inferring DSP48 slices in Verilog

Evaluating Polynomials in an FPGA

Sometimes, a polynomial will need to be evaluated at a specific value in an algorithm.  This might be used for curve fitting or interpolation.  Another case is for Galois Fields and error correction, where high-degree polynomials are common.  There is … Continue reading

Posted in FPGA, Math | Tagged | Comments Off on Evaluating Polynomials in an FPGA

Reed Solomon Decoder, Forney’s Equation

In the previous articles, I described how to find the syndromes, the error locater polynomial, and the roots of that polynomial.  The last bit of information needed is the error magnitudes.  Forney’s equation can be used to determine this. 

Posted in FPGA | Tagged | Comments Off on Reed Solomon Decoder, Forney’s Equation

Reed Solomon Decoder, Chein Search

The Berlekamp-Massey algorithm provides an error locater polynomial.  Similar to the syndromes, this polynomial doesn’t provide the required information directly.  Instead, it is the multiplicative inverse of the roots of this polynomial that correspond to the error locations.  Just like … Continue reading

Posted in FPGA | Tagged | Comments Off on Reed Solomon Decoder, Chein Search

Reed Solomon Decoder, Berlekamp-Massey

Given a sequence of syndromes, the Berlekamp-Massey algorithm determines an LFSR that could generate this sequence.  This helps explain how the syndromes can both find and correct errors.  The locations of errors are based on the pattern behind the syndromes.  … Continue reading

Posted in FPGA | Tagged | Comments Off on Reed Solomon Decoder, Berlekamp-Massey

Reed Solomon Decoder, Syndromes

As mentioned, the first part of my Reed-Solomon decoder implementation is the calculation of syndromes.  This is a straightforward process that only requires a large amount of parallel processing. 

Posted in FPGA | Tagged | Comments Off on Reed Solomon Decoder, Syndromes

Reed Solomon Decoder, Overview

Recently, I had written a Reed-Solomon encoder module out of curiosity.  The next step was to write the decoder.  The resulting decoder was written to work with my encoder — allowing a valid input every cycle.  The project was very … Continue reading

Posted in FPGA | Tagged , | Comments Off on Reed Solomon Decoder, Overview