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Monthly Archives: August 2010
The Magic LFSR Taps
Just like magic, these aren’t real either. Continue reading
Variables are not Signals
Annoying and Dangerous when misused. Continue reading
Posted in VHDL
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Hold Violations
A hold violation occurs when the data into a system changes too soon after a clock edge. Many standards and ICs specify significantly positive hold times. Failure to meet these hold times can result in unpredictable behavior.
Posted in Fundamentals
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Negative Setup Time
These registers have not enlisted the aid of a prominent psychic. Continue reading
Posted in Fundamentals
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The Synthesizer Thanks You For Your Opinion
The synthesizer thanks you for your opinion but has decided to go in another direction. The problem of trying to infer a specific implementation. Continue reading
Posted in FPGA
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The Carry-Select Method
One method that can be used to optimize a design for performance is based on the carry-select adder. The general idea is that an adder can either have a carry-in of 0, or a carry-in of 1. Two adders can … Continue reading
Why Asynchronous Signals are Dangerous
The careless use of asynchronous signals can lead to unpredictable operation at any clock frequency. Continue reading
Posted in Fundamentals
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Logically Good, Actually Bad
Often, things that sound like they should work well, but actually don’t. This actually is related to one of my rules — “avoid excessively creative code.” In this case, I decided to compare the fancy “carry-lookahead” adder to whatever fabric-based … Continue reading
Posted in FPGA
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